1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a gate conductor with opposed sidewall surfaces upon which a spacer is formed having a tapering profile that is less susceptible to accumulation of a silicide-forming metal.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Conventional transistor formation involves implantation of a light concentration of dopant self-aligned to the gate conductor followed by implantation of a heavier concentration of dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped drain ("LDD") section within the active area (i.e., junction) at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. The second implant dose forms a heavily doped source/drain region within the junction laterally outside the LDD section.
A transistor employing sidewall spacers formed using the technique described above is depicted in FIG. 1. A gate conductor 24 is spaced above a semiconductor substrate 20 by a gate oxide 22. Dielectric sidewall spacers 28 are arranged upon the opposed sidewall surfaces of gate conductor 24. Spacer 28 may be composed of, for example, silicon dioxide ("oxide") or silicon nitride ("nitride"). LDD areas 26 are disposed within substrate 20 directly underneath sidewall spacers 28. Source/drain regions 30 are arranged within substrate 20 laterally adjacent LDD areas 26. The profile of each of the sidewall spacers 28 tapers away from an adjacent sidewall surface of gate conductor 24 as it approaches the surface of substrate 20. As such, the profile of the leftmost spacer is positively sloped, and the profile of the rightmost spacer is negatively sloped. This configuration of sidewall spacers 28 is a result of the etch technique used to define the spacers. Typically, a plasma etch technique is employed that is anisotropic in nature so as to promote more frequent ion bombardment upon vertical surfaces than horizontal surfaces of the spacer material. Unfortunately, ion bombardment is typically not completely anisotropic, and some ions manage to strike exposed vertical surfaces. Thus, during the formation of oxide sidewall spacers 28, corner regions of the dielectric being etched are attacked from two directions. The exposed surfaces of the resulting sidewall spacers 28 are thus non-vertical. The sidewall spacers 28 have a varying thickness which increases from the top to the bottom of the spacers.
Integrated circuit formation involves electrical linkage of various active devices, i.e., transistors. Ohmic contacts are formed in contact "windows" that extend through an interlevel dielectric to silicon-based junctions and/or polycrystalline silicon ("polysilicon") gates of transistors, and multiple levels of dielectrically isolated interconnect are routed to the contacts. In order to form highly conductive ohmic contacts in the windows between transistors and overlying interconnect, it is oftentimes necessary to incorporate a layer of refractory metal at the junctures. The refractory metal, when subjected to a sufficient temperature, reacts with the underlying silicon in the contact window to form a low resistivity "silicide". Any unreacted metal is removed after formation of the silicide. Since the silicide reaction occurs wherever refractory metal is in contact with a region heavily concentrated with silicon, a self-aligned silicide ("salicide") results exclusively upon silicon-based junctions and polysilicon gates.
FIG. 2 depicts the physical vapor deposition ("PVD") of a refractory metal layer 32, e.g., titanium, from a metal target onto exposed surfaces of the semiconductor topography depicted in FIG. 1. Since PVD is a line-of-sight process in which deposition occurs upon the first encountered surface, the step coverage of refractory metal layer 32 is dependent on the orientation of the underlying topological features. Dependency on the orientation is often referred to as a "collimated" deposition in that columns of deposited material generally accumulate perpendicular to horizontally oriented topological surfaces. Therefore, the tapering, non-vertical profiles of sidewall spacers 28 permit deposited metal to accumulate upon the exposed surfaces of the spacers. As further illustrated in FIG. 2, refractory metal layer 32 may be exposed to an anneal cycle 34 in order initiate reaction between the metal and underlying silicon to form silicide.
As shown in FIG. 3a, a silicide 36 is formed upon source/drain regions 30 and the upper surface of gate conductor 24. The anneal cycle 34 is performed at relatively high temperatures above 600.degree. C., and thus promotes cross-diffusion of silicon atoms in spacers 28 and metal atoms in refractory metal layer 32. FIG. 3b depicts a detailed view along section 3b of FIG. 3a. Some of the silicon atoms 40 of spacer 28 have bonded to metal atoms 38 to form silicide in close proximity to the surface of spacer 28. Unfortunately, the presence of silicide in spacers 28 may lead to capacitive coupling or formation of a fully conductive path between polysilicon gate conductor 24 and adjacent source/drain regions 30. This undesirable phenomenon is often referred to as silicide shorting or "bridging".
Many researchers and manufacturers advocate a multiple step silicide formation process to help address the bridging problem. First, a refractory metal, such as titanium is deposited over the entire topography. Next, the metal is heated to a low temperature in the presence of a nitrogen ambient to form a reacted, relatively high resistance silicide in the contact windows. The unreacted metal is then removed using a wet chemical etch (e.g., NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O) while retaining reacted metal or metal silicide in the contact windows. Finally, a higher temperature anneal is performed in order to produce a lower resistivity silicide in regions where the metal has previously reacted.
The two-step anneal process is not always successful, especially if the anneal temperature cycles are not carefully monitored and controlled. If the first anneal temperature is too high, then the sidewall spacers might be partially consumed and/or metal atoms might readily migrate into the spacers where they can bond with silicon atoms to deleteriously cause silicide shorting. Thus, the first anneal temperature must be carefully maintained and is highly dependent on the thickness of titanium across the spacer sidewall. Moreover, extraction of the wafer and the reacted metal silicide in the interim between the two step anneal process may place impurities or native oxides in the contact window above the gate conductor and the source/drain regions.
It is therefore desirable that a semiconductor fabrication process be developed which need not be concerned with silicide bridging. More specifically, a process is needed in which refractory metal is altogether absent from the sidewall spacers arranged upon opposed sidewall surfaces of a transistor gate conductor. If refractory metal is prevented from contacting the sidewall spacers, silicon atoms in the spacers would have no metal atoms with which to bond and form silicide. Substantially minimizing, if not eliminating, metal from the sidewall spacers would lessen the concerns associated with high temperature anneal cycles and two-step anneal cycles.